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-- Company: 
-- Engineer: 
-- 
-- Create Date:    16:19:40 03/18/2011 
-- Design Name: 
-- Module Name:    mux_sum - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity mux_sum is
    Port ( enable 		 : in  STD_LOGIC;
           instr_reg_out : in  STD_LOGIC_VECTOR (17 downto 0); --offset multiplexor
           pc_out 		 : in  STD_LOGIC_VECTOR (9 downto 0); --pc_out
           s      		 : out STD_LOGIC_VECTOR (9 downto 0));
end mux_sum;

architecture RTL of mux_sum is
signal buffer_2 : STD_LOGIC_VECTOR (9 downto 0);

alias offset : STD_LOGIC_VECTOR (7 downto 0) is instr_reg_out (7 downto 0);

	begin
	buffer_2 <= EXT(offset,10);

	s <=	buffer_2 + pc_out when (enable = '0') else
			EXT("1",10) + pc_out; --sumar todo unos
end RTL;

